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Lab Project Solution Nanyang Technological University, Singapore

Introduction

The project consists of 3 parts and a bonus assignment. You are required to do coding and synthesis, and to demonstrate each part of the project. Write a project report to briefly describe the working of the design of each part. Report should also include the timing report and the waveform generated by simulating the testbench of each part of the project. For Part-3 and bonus assignment you will be required to find the minimum execution time and the reduction CPI which you achieve for the given program.


Project Part-1

Modify the 4-stage pipelined processor of Lab-3 to include BEQ, LW, and SW instructions and convert that to a 5-stage pipelined processor. (6 marks)

Project Part-2

Modify the processor designed in Part-1 of the project to include jump register (jr), jump (J), and jump & link (jal) instructions. (5 marks)

Project Part-3

Each group of students will be given a program which gets slowed due to pipeline stalls. You are required to modify the program to remove the hazards so as to reduce the number of pipeline stalls. Finally, you will estimate the reduction in the CPI and execution time which you achieve. (4 marks)

Bonus Assignment

You will be required to incorporate a direct-mapped cache for data memory (DM). This is an optional assignment. You will not loose any mark if you cannot complete this. On Bonus Part of the project you will be awarded with maximum of 5 marks over and above what you have secured in this lab project such that the total marks secured in course work will not exceed 30 marks for any student.

Deadline

Report is to be submitted by 11th November 2015 before 5 pm at
Hardware Projects Lab.

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